FPGA Implementation of Double Precision Floating Point Multiplier using Xilinx Coregen Tool

Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. The main applications of floating points today are in the field of medical imaging, biometrics, motion capture and audio applications. The IEEE floating point standard defines both single precision and double precision formats. Multiplication is a core operation in many signal processing computations, and as such efficient implementation of floating point multipliers is an important concern. Until now there is the implementation of the low precision floating point formats, but this piece of work considers the implementation of 64-bit double precision multiplier. This paper presents the FPGA implementation of double precision floating point multiplier using Xilinx Coregen Tool. KeywordsField Programmable Gate Array, Multiplier, Single Precision, Double Precision.